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general description the max6916 provides all the features of a real-timeclock (rtc) plus a microprocessor supervisory circuit, nv ram controller, and backup-battery monitor func- tion. in addition, 96 x 8 bits of static ram are available for scratchpad storage. the max6916 communicates with a microprocessor through an spi-bus-compati- ble serial interface. the real-time clock/calendar provides seconds, min- utes, hours, day, date, month, and year information. the end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap years through 2099. the clock operates in either 24hr or 12hr format with an am/pm indicator. a time/date-programmable alarm function is provided with an open-drain, active-low alarm output. the microprocessor supervisory circuit features an open-drain, active-low reset available in three different reset thresholds. a manual reset input and a watchdog function are included as well. the nv ram controller provides power for external sram from a backup battery plus chip-enable gating. the back- up battery also provides data retention of the on-board 96 x 8 bits of ram. an open-drain, active-low, battery-on sig- nal alerts the system when operating from a battery. the battery-test circuitry periodically tests the backup battery for a low-battery condition. an optional external resistor network selects different battery thresholds. a freshness seal prevents battery drain until the first v cc power-up.the max6916 has a crystal-fail-detect circuit and a data-valid bit. the max6916 is available in a 20-pin qsop package and is guaranteed to operate over the -40? to +85? extended temperature range. applications point-of-sale equipmentprogrammable logic controllers intelligent instruments fax machines digital thermostats industrial controls features ? real-time clock counts seconds, minutes, hours, date, month, day of week, and year with leap-year compensation through 2099 ? 4mhz spi-bus-compatible interface at 5v, 2mhzat 3v, and 3.3v ? spi interface supports modes 1 and 3 (0, 1 and 1, 1) ? 96 x 8 bits of ram for scratchpad data storage ? uses standard 32.768khz, 6pf load, watchcrystal ? single-byte or multiple-byte (burst mode) datatransfer for read or write of clock registers or ram ? battery monitor and low-battery warning output internal default for lithium backup-batterytesting pins available for other backup-battery testing configurations ? dual power-supply pins for primary and backuppower ? battery-on output ? nv ram controller chip-enable gating (control of ce with reset and power valid)v out for sram power ? p supervisor with watchdog input ? programmable time/date alarm output ? data valid bit (loss of all voltage alerts user ofcorrupt data) ? crystal-fail detect ? small 20-pin, qsop surface-mount package max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ________________________________________________________________ maxim integrated products 1 ordering information 19-3694; rev 0; 10/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package pkg code max6916eo30+ -40 c to +85 c 20 qsop e20-2 max6916eo33+ -40 c to +85 c 20 qsop e20-2 MAX6916EO50+ -40 c to +85 c 20 qsop e20-2 pin configuration and selector guide appear at end of datasheet. spi is a trademark of motorola, inc. + denotes lead-free package. downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics(v cc = v cc(min) to v cc(max) , t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (notes 1, 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v batt , v cc to gnd ...............................................-0.3v to +6.0v all other pins to gnd.................................-0.3v to (v cc + 0.3v) all other pins to gnd..............................-0.3v to (v batt + 0.3v) input currents v cc ............................................................................200ma v batt ...........................................................................20ma gnd ..............................................................................20ma all other pins ..............................................................?0ma output currents v out continuous .........................................................200ma all other outputs ...........................................................20ma continuous power dissipation (t a = +70 c) 20-pin qsop (derate 9.1mw/ c over +70 c).............727mw operating temperature range ...........................-40 c to +85 ? junction temperature ......................................................+150 ? storage temperature range .............................-65 c to +150 ? lead temperature (soldering, 10s) .................................+300 ? parameter symbol conditions min typ max units max6916eo30 2.7 3.0 3.3 max6916eo33 3.0 3.3 3.6 operating voltage range(note 3) v cc MAX6916EO50 4.5 5.0 5.5 v max6916eo30 2.0 5.5 max6916eo33 2.0 5.5 operating voltage range batt(note 4) v batt MAX6916EO50 2.0 5.5 v v batt = 2v, v cc = 0 1 v batt = 3v, v cc = 0 1.4 v batt = 3.6v, v cc = 0 1.9 xtal faildisabled v batt = 5.5v, v cc = 0 3.8 v batt = 2v, v cc = 0 1.23 v batt = 3v, v cc = 0 1.61 v batt = 3.6v, v cc = 0 2.3 timekeeping current v batt (note 5) i batt xtal failenabled v batt = 5.5v, v cc = 0 4.08 ? v cc = 3.3v, v batt = 0 0.35 v cc = 3.6v, v batt = 0 0.4 xtal faildisabled v cc = 5.5v, v batt = 0 1.1 v cc = 3.3v, v batt = 0 0.36 v cc = 3.6v, v batt = 0 0.42 active supply current v cc (note 6) i cca xtal failenabled v cc = 5.5v, v batt = 0 1.2 ma v cc = 3.3v, v batt = 0 20 v cc = 3.6v, v batt = 0 25 xtal faildisabled v cc = 5.5v, v batt = 0 76 v cc = 3.3v, v batt = 0 27 v cc = 3.6v, v batt = 0 30 standby current v cc (note 5) i ccs xtal failenabled v cc = 5.5v, v batt = 0 81 ? downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller _______________________________________________________________________________________ 3 dc electrical characteristics (continued)(v cc = v cc(min) to v cc(max) , t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (notes 1, 2) parameter symbol conditions min typ max units v out v cc = 2.7v, v batt = 0, i out = 35ma v cc - 0.2 v cc = 3.0v, v batt = 0, i out = 35ma v cc - 0.2 v out in v cc mode (note 4) v out v cc = 4.5v, v batt = 0, i out = 70ma v cc - 0.2 v v batt = 2v, v cc = 0, i out = 400? v batt - 0.02 v batt = 3v, v cc = 0, i out = 800? v batt - 0.03 v out in battery-backup mode (notes 4, 7) v out v batt = 4.5v, v cc = 0, i out = 1.5ma v batt - 0.05 v v batt -to-v cc switchover threshold v tru power-up (v cc < v rst ) switch from v batt to v cc (note 7) v batt + 0.1 v v cc -to-v batt switchover threshold v trd power-down (v cc < v rst ) switch from v cc to v batt (note 7) v batt - 0.1 v ce_in and ce_out (figures 7, 11, 12, 13) ce_in leakage current i il , i ih disabled, v cc < v rst , v ce_in = v cc or gnd -1 +1 ? ce_in -to- ce_out resistance v cc = v cc(min) , v ih = 0.9v cc , ce_out = gnd, v il = 0.1v cc , ce_out = v cc 46 140 ce_in -to- ce_out propagation delay t ced 50 source impedance driver, c load = 10pf, v cc = v cc(min) , v ih = 0.9v cc , v il = 0.1v cc (note 8); measured from 50% point once_in to the 50% point of ce_out 10 20 ns reset active to ce_out high delay t rce mr high to low 2 10 50 ? ce_out active-low delay after v cc > v rst t rp 140 200 280 ms ce_out output high voltage v oh i oh = -100?, v batt = 2v, v cc = 0, reset = low 0.8 x v batt v mr input (figure 7) v il 0.8 mr input voltage v ih 2.0 v mr pullup resistance internal pullup resistor 50 k mr minimum pulse width 1 s mr glitch immunity t gw 35 ns mr to reset delay t rd v cc = v cc(min) , v batt = 0 450 600 ns downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 4 _______________________________________________________________________________________ dc electrical characteristics (continued)(v cc = v cc(min) to v cc(max) , t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (notes 1, 2) parameter symbol conditions min typ max units wdi input (figure 9) wdi initial timeout period v cc > v rst from rising edge of reset 1.00 1.6 2.25 s t wdl long watchdog timeout period 1.00 1.6 2.25 s watchdog timeout period t wds short watchdog timeout period 140 200 280 ms minimum wdi input pulse width t wdi 100 ns v il 0.8 v wdi input threshold v ih 2.0 wdi input leakage current v wdi = v cc or gnd -100 +100 na v cc standby current with wdi max frequency i ccsw watchdog frequency = 1mhz,v cc = v cc(max) (note 5) 450 ? battery test and trip (figures 14, 15, and 16) v batt trip point v btp internal mode 2.45 2.6 2.7 v trip input threshold v trip v cc = v cc(max) , v batt = 2v, external mode 1.14 1.24 1.31 v trip input comparatorhysteresis v trip_hyst 10 mv trip input current i trip_lkg external mode -100 +100 na battery test load r load_int internal 0.5 0.91 1.3 m test output high voltage v test_hig h i test = -5ma v out - 0.3v v test output low voltage v test_low i test = 5ma 0.3 v batt_lo , alm output v ol v batt = 2v, v cc = 0, i ol = 5ma 0.5 v ol v cc = 2.7v, v batt = 0, i ol = 10ma 0.5 output low voltage v ol v cc = 4.5v, v batt = 0, i ol = 20ma 0.5 v off-leakage i lkg -100 +100 na batt_on output v ol v batt = 2v, v cc = 0, i ol = 5ma 0.5 v ol v batt = 2.7v, v cc = 0, i ol = 10ma 0.5 output low voltage v ol v batt = 4.5v, v cc = 0, i ol = 20ma 0.5 v off-leakage i lkg -100 +100 na reset max6916eo30 2.5 2.63 2.7 max6916eo33 2.8 2.93 3.0 reset threshold voltage v rst MAX6916EO50 4.1 4.38 4.5 v v rst hysteresis v hyst 30 mv m ax 6916e o 30 27 75 m ax 6916e o 33 37 90 v cc falling-reset delay t rpd v c c fal l i ng fr om v rs t ( m ax ) to v rs t ( m in ) m easur ed fr om the b eg i nni ng of v c c fal l i ng to res et l ow m ax 6916e o 50 50 120 ? downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller _______________________________________________________________________________________ 5 dc electrical characteristics (continued)(v cc = v cc(min) to v cc(max) , t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (notes 1, 2) parameter symbol conditions min typ max units m ai n reset acti ve- ti m eout p er i od t rp 140 200 280 ms reset output-low voltage v ol reset asserted, i ol = 1.6ma, v batt = 2v, v cc = 0 0.2 v off-leakage i lkg -100 +100 na spi digital inputs din, sclk, cs input high voltage v ih 2v input low voltage v il 0.8 v input hysteresis v hys 0.05 x v cc v input leakage current v in = 0 to v cc -100 +100 na input capacitance (note 8) 10 pf spi digital output dout output high voltage v oh i oh = -1.6ma 0.9 x v cc v output low voltage v ol i ol = 1.6ma 0.4 v output capacitance (note 8) 10 pf output off-state leakage current i oz -100 +100 na ac electrical characteristics(v cc = v cc(min) to v cc(max) , t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units spi bus timing (figure 2 (note 9)) maximum-input rise time t rin din, sclk, cs 2 s maximum-input fall time t fin din, sclk, cs 2 s output rise time t rout dout, c load = 100pf 10 ns output fall time t fout dout, c load = 100pf 10 ns max6916eo30, max6916eo33 500 slck period t cp MAX6916EO50 238 ns max6916eo30, max6916eo33 200 sclk high time t ch MAX6916EO50 100 ns max6916eo30, max6916eo33 200 sclk low time t cl MAX6916EO50 100 ns sclk fall to dout valid t do c load = 100pf 100 ns din-to-sclk setup time t ds 100 ns din-to-sclk hold time t dh 0n s sclk rise to cs rise hold time t csh 0n s cs high pulse width t csw 200 ns cs high-to-dout high impedance t csz 100 ns cs to sclk setup time t css 100 ns battery test timing (figure 15) battery test to batt_lo active t bl (note 8) 1 s downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 6 _______________________________________________________________________________________ note 1: v rst is the reset threshold for v cc . see the ordering information . note 2: all parameters are 100% tested at t a = +85 c. limits over temperature are guaranteed by design and are not production tested. note 3: the spi serial interface is operational for v cc > v rst . note 4: see the detailed description (v out function). note 5: i ccs is specified with cs = v cc , sclk = din = wdi = ce_in = gnd, dout, v out , ce_out , and mr floating. i batt is specified with wdi = ce_in = sclk = din = gnd, cs = v cc , dout, v out , ce_out , and mr floating. note 6: i cca is specified with sclk = 4mhz for v cc = +5.5v and sclk = 2mhz for v cc = +3.3v and +3.6v. dout = open, cs = gnd, din = v cc , ce_in = v cc , v out and ce_out open, wdi = v cc or gnd. note 7: for out switchover to batt, v cc must fall below v rst and v batt . for out switchover to v cc , v cc must be above v rst or above v batt . note 8: guaranteed by design. not subject to production testing. note 9: all values are referred to v ih(min) and v il(max) levels. v cc -to-out voltage vs. temperature max6916 toc01 temperature ( c) v cc -to-out voltage (mv) 60 35 10 -15 17.5 20.0 22.5 25.0 27.5 30.015.0 -40 85 v cc = 3v v batt = 0v i out = 35ma v cc = 3.3v v batt = 0v i out = 35ma batt-to-out voltage vs. temperature batt-to-out voltage (mv) 1 2 3 4 5 6 7 8 9 10 0 max6916 toc02 temperature ( c) 60 35 10 -15 -40 85 v cc = 0v v batt = 3v i out = 800 a v cc = 0v v batt = 2v i out = 400 a timekeeping current vs. temperature i batt ( a) 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.80.8 max6916 toc03a temperature ( c) 60 35 10 -15 -40 85 sclk = gnd, dout = opencs = v cc , din = gnd ce_in = gndxtal fail enabled timekeeping current vs. temperature i batt ( a) 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.80.8 max6916 toc03b temperature ( c) 60 35 10 -15 -40 85 sclk = gnd, dout = opencs = v cc , din = gnd ce_in = gndxtal fail disabled typical operating characteristics (v cc = 3.3v, v batt = 3v, t a = +25 c, unless otherwise noted.) ac electrical characteristics (continued)(v cc = v cc(min) to v cc(max) , t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units battery test cycle normal t btcn (note 8) 24 hr battery test pulse width t btpw (note 8) 1 s downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller _______________________________________________________________________________________ 7 reset timeout period (ms) 190 200 210 220 230 240180 reset timeout period vs. temperature max6916 toc04 temperature ( c) 60 35 10 -15 -40 85 reset comparator delay vs. v cc falling max6916 toc05 v cc falling (v/ms) reset delay ( s) 100 10 1 10 100 1000 1 0.1 1000 reset comparator delay ( s) 10 15 20 25 30 35 40 45 50 5 reset comparator delay vs. temperature max6916 toc06 temperature ( c) 60 35 10 -15 -40 85 v cc falling at 10v/ms reset threshold vs. temperature (max6916eo33) reset threshold (v) 2.900 2.925 2.950 2.975 3.0002.875 max6916 toc07 temperature ( c) 60 35 10 -15 -40 85 reset goes high abovethis threshold reset goes low belowthis threshold watchdog timeout period vs. temperature watchdog timeout period (ms) 190 200 210 220 230 240180 max6916 toc08 temperature ( c) 60 35 10 -15 -40 85 wd time bit set to 1 maximum transient duration vs. reset comparator overdrive max6916 toc09 overdrive (mv) maximum transient duration ( s) 450 400 150 200 250 300 350 30 40 50 60 70 80 90 100 20 100 500 reset asserts above this line chip-enabled propagation delay vs. ce_out load capacitance (max6916eo33) max6916 toc10 load capacitance (pf) chip-enabled propagation delay (ns) 90 80 10 20 30 50 60 40 70 1 2 3 4 5 6 7 80 0 100 rising edge of ce_in torising edge of ce_out v cc = 3v v cc = 5v v cc = 3.3v chip-enabled propagation delay vs. ce_out load capacitance (max6916eo33) max6916 toc111 load capacitance (pf) chip-enabled propagation delay (ns) 90 80 10 20 30 50 60 40 70 1 2 3 4 5 6 7 80 0 100 falling edge of ce_in tofalling edge of ce_out v cc = 3v v cc = 5v v cc = 3.3v active supply current vs. supply voltage max6919 toc12 supply voltage (v) i cca (ma) 5.1 4.7 3.9 4.3 3.5 3.1 0.125 0.150 0.175 0.200 0.225 0.250 0.275 0.300 0.325 0.350 0.375 0.4000.100 2.7 5.5 sclk - 2mhz, dout = opencs = gnd, din = ce_in = v cc xtal fail enabled t a = +85 c t a = +25 c t a = -40 c typical operating characteristics (continued) (v cc = 3.3v, v batt = 3v, t a = +25 c, unless otherwise noted.) downloaded from: http:///
typical operating characteristics (continued) (v cc = 3.3v, v batt = 3v, t a = +25 c, unless otherwise noted.) max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 8 _______________________________________________________________________________________ active supply current vs. supply voltage max6919 toc13 supply voltage (v) i cca (ma) 5.1 4.7 3.9 4.3 3.5 3.1 0.125 0.150 0.175 0.200 0.225 0.250 0.275 0.300 0.325 0.350 0.375 0.4000.100 2.7 5.5 sclk - 2mhz, dout = opencs = gnd, din = ce_in = v cc xtal fail disabled t a = +85 c t a = +25 c t a = -40 c timekeeping current vs. supply voltage v batt (v) i batt (ma) max6916 toc14 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 sclk = gnd, dout = opencs = v cc , din = gnd ce_in = gndxtal fail enabled t a = +85 c t a = +25 c t a = -40 c timekeeping current vs. supply voltage v batt (v) i batt (ma) max6919 toc15 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 t a = +85 c t a = +25 c t a = -40 c sclk = gnd, dout = opencs = v cc , din = gnd ce_in = gndxtal fail disabled v cc to v out drop vs. output current (normal mode) max6916 toc16 output current (ma) v cc to v out drop (v) 90 80 70 60 50 40 30 20 10 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0 01 0 0 v cc = +2.7v v cc = +3.3v v cc = +5v v batt to v out drop vs. output current (battery backup mode) max6916 toc17 output current (ma) v batt to v out drop (v) 2.0 1.6 1.2 0.8 0.4 0.005 0.010 0.015 0.020 0.025 0 0 2.4 v batt = +3.3v v batt = +2v v batt = +5v downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller _______________________________________________________________________________________ 9 pin description pin name function 1v out supply output for external sram or other ics requiring use of backup battery power. when v cc rises above the reset threshold or above v batt , v out is connected to v cc . when v cc falls below v reset and v batt , v batt is connected to v out . connect a 0.1? low-leakage bypass capacitor from v out to gnd. leave open if not used. 2 test external battery test. active high for 1s during each battery test. intended to drive an external mosfetor bipolar transistor for an external battery-test configuration. external test must be selected in the control register to use test; otherwise, it remains low. leave open if not used. 3 trip external trip set. if a different battery-low threshold is desired other than the internal por default of v btp , then connect r set+ between v batt and trip and r set- between trip and the drain or collector of an external transistor whose base or gate is connected to test; see figure 14 (see the battery test section). external test must be selected in the control register to use trip. leave open if not used. 4 batt_on open-drain, battery-on indicator. batt_on is active low when the max6916 is powered from v batt . 5 ce_in chip-enable input. the input to the chip-enable gating circuitry. connect ce_in to gnd if unused. 6 mr manual-reset input. a logic-low on mr asserts reset . reset remains asserted as long as mr is low and for t rp after mr returns high. the active-low mr input has an internal pullup resistor. mr can be driven from a ttl- or cmos-logic line or shorted to ground with a switch. internal debouncing circuitryensures noise immunity. leave mr open if unused. 7 wdi watchdog input. if wdi remains either high or low for longer than the watchdog timeout period, theinternal watchdog timer runs out and reset is asserted. the internal watchdog timer clears while reset is asserted or when wdi sees a rising or falling edge. the watchdog function can be disabled from thecontrol register. the timeout period is configurable in the control register for 200ms or 1.6s. 8 gnd ground 9 x1 32.768khz crystal-oscillator input 10 x2 32.768khz crystal-oscillator output downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 10 ______________________________________________________________________________________ detailed description functional description the max6916 contains eight 8-bit timekeeping registers,seven 8-bit alarm threshold registers, one status register, one control register, one alarm-configuration register, and 96 x 8 bits of sram. in addition to single-byte reads and writes to registers and ram, there is a burst timekeeping register read/write command, a burst ram read/write command, and a battery-test command that allows soft- ware-commanded testing of the backup battery at any time. an spi-bus-compatible interface allows serial com- munication with a microprocessor. when v cc is less than the reset threshold, the serial interface is disabled to pre- vent erroneous data from being written to the max6916. a microprocessor supervisory section and an nvram controller are provided for ease of implementation with microprocessor-based systems. a crystal-fail-detect cir- cuit and a data-valid bit can be used to guarantee ram data integrity and valid timekeeping data. time and cal- endar data are stored in a binary-coded decimal (bcd) format. figure 1 shows the functional diagram of the max6916. real-time clock the rtc provides seconds, minutes, hours, day, date,month, and year information. the end of the months is automatically adjusted for months with fewer than 31 days, including corrections for leap years through 2099. crystal oscillator the max6916 uses an external, standard 6pf loadwatch crystal. no other external components are required for this timekeeping oscillator. power-up oscil- lator start time is dependent mainly upon applied v cc and ambient temperature. the max6916, because ofits low timekeeping current, exhibits a typical startup time of 1s to 2s. spi-compatible interface interface the max6916 to a microcontroller using a 4-wire, serial peripheral interface (spi). the spi is a synchronous bus for address and data transfer and is used when interfacing with motorola and other micro- controllers with an spi port. four connections are required for the interface: dout (serial data out), din (serial data in), sclk (serial clock), and cs (chip select). the max6916 acts as a slave device and the pin description (continued) pin name function 11 din spi serial bus data input 12 cs spi serial bus chip-select input. drive cs low to initiate a data transfer. 13 dout spi serial bus data output 14 sclk spi serial bus clock input 15 alm open-drain, active-low alarm output. alm goes low when rtc time matches alarm thresholds set in the alarm threshold registers. alm stays low until cleared by reading or writing to the alarm configuration register or to any of the alarm threshold registers. 16 ce_out chip-enable output. ce_out goes low only when ce_in is low and reset is not asserted. if ce_in is low when reset is asserted, ce_out remains low for t rce or until ce_in goes high, whichever occurs first. ce_out is pulled to v out . 17 batt_lo open-drain, battery-low indicator. batt_lo is active low when the v batt input is tested below v btp if the internal trip is selected in the control register (por default). if external trip is selected in the controlregister, then batt_lo is active low when trip is less than v trip . 18 reset open-drain, active-low reset output. reset pulses low for t rp when triggered, and stays low whenever v cc is below the reset threshold or when mr is logic-low. reset remains low for t rp after either v cc rises above the reset threshold or mr goes from low to high. 19 v cc main supply input. connect a 0.1? bypass capacitor from v cc to gnd. 20 v batt backup-battery input. when v cc falls below the reset threshold and v batt , v out switches from v cc to v batt . when v cc rises above v batt or the reset threshold, v out reconnects to v cc . v batt may exceed v cc . connect v batt to gnd if no backup-battery supply is used. connect a 0.1? low-leakage bypass capacitor from v batt to gnd. downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 11 watchdog timer debounce circuit reset logic reset ce control ce_out oscillator 32.768khz crystal- fail detect dividers seconds minutes hours date month day year control century alarm config batt test status config alarm thresholds clock burst ram burst power control and monitor control logic input- shift registers address register 96 x 8 ram data valid logic alarm control logic xtal fail max6916 wdi mr x1x2 ce_in test trip gnd v batt v out v cc batt_lo batt_on sclk cs din dout alm figure 1. functional diagram downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 12 ______________________________________________________________________________________ microcontroller acts as the master in an spi application.cs is asserted low by the microcontroller to initiate a transfer and deasserted high to terminate a transfer.din transfers input data to the max6916 from the microcontroller, and dout transfers output data from the max6916 to the microcontroller. sclk is used to synchronize data movement between the microcon- troller and the max6916. sclk, which is generated by the microcontroller, is active only during address and data transfer to any device on the spi bus. the inactive clock polarity is usually programmable on the micro- controller side of the spi interface. for the max6916, input data (din) is latched on the positive edge and output data (dout) is shifted out on the negative edge. there is one clock for each bit transferred. address and data bits are transferred in groups of eight. figure 2 shows an spi bus timing diagram. the spi protocol allows for one of four combinations of serial clock phase and polarity from the microcontroller, through a 2-bit selection in its spi control register. the clock polarity is specified by the cpol control bit, which selects active-high or active-low clock, and has no significant effect on the transfer format. the clock- phase control bit, cpha, selects one of two different transfer formats. the clock phase and polarity must be identical for the master and the slave. for the max6916, set the control bits to cpha = 1 and cpol = 1. this setting configures the system for data to be launched on the negative edge of sclk and sampled on the positive edge. with cpha equal to 1, cs can remain low between successive data byte transfers,allowing burst-mode data transfers to occur. address and data bytes are shifted, most significant bit(msb) first, into the serial data input din of the max6916 and out of the serial data output dout. data is shifted out at the negative edge of sclk and shifted in or sampled at the positive edge of sclk. any trans- fer requires the address of the byte to be followed by 1 or more bytes of data. data is transferred out of dout for a read operation and into din for a write operation. when not transferring data out, dout is put into a high- impedance state (figure 2). to maximize battery life and prevent erroneous data from being entered into the max6916, the serial bus interface is disabled when v cc is below v rst or when reset is active. in order to initiate spi communications with themax6916, cs needs to be driven low, after which an address/command byte must be input. theaddress/command byte specifies the register to or from which information is to be transferred, as well as the nature of the transfer (read or write). after the address/command byte, 1 or more data bytes can be written or read. for a single-byte transfer, 1 byte is writ- ten or read and then cs is driven high by the microcon- troller (figures 3 and 5). for a multiple-byte transfer,however, multiple bytes can be read or written to the max6916 after the address/command byte has been written (figures 4 and 6). in the case of burst operation, each read or write cycle causes the rtc register or ram address to automatically increment. incrementing continues (maximum value is 96 for ram and 8 for reg- ister bank) until spi transmission is terminated. to ter- minate the spi transmission, drive cs high. cs sclk din dout t css t ch t dh t ds d7 d6 d5 d0 d7 d0 t cp t do t csw t csh t csz t cl figure 2. spi bus timing diagram downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 13 address/command byte each data transfer into or out of the max6916 is initiat- ed by an address/command byte. the address/com- mand byte specifies which registers are to be accessed, and if the access is a read or write. the address command byte is input msb (bit 7) first. bit 7 determines if a read (logic 1) or write (logic 0) takesplace. data transfers can occur 1 byte at a time or in multiple-byte burst mode. bits 6 0 specify the desig- nated register or ram location to be read or written to.figures 3, 4, 5, and 6 show the different transfer opera- tions that can take place with the max6916. cs sclk din dout a6 a5 a4 a3 a2 a1 a0 d6 d5 d4 d3 d2 d1 d0 d7 0 address/command byte data byte single write dout is high impedance; there is no activity on dout during writes figure 3. spi interface single write cs sclk din dout a5 a4 a3 a2 a1 a0 d6 d5 d4 d3 d2 d1 d0 d7 0 address/command byte data byte 1 burst write a6 data byte n d6 d5 d4 d3 d2 d1 d0 d7 dout is high impedance; there is no activity on dout during writes figure 4. spi interface multiple/burst write cs sclk din dout a6 a5 a4 a3 a2 a1 a0 1 address/command byte data byte single read d6 d5 d4 d3 d2 d1 d0 d7 dout is high impedance figure 5. spi interface single read downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 14 ______________________________________________________________________________________ chip select ( cs ) cs serves two functions. first, cs turns on the control logic that allows access to the shift register foraddress/command and data transfer. second, cs pro- vides a method of terminating either single-byte or mul-tiple-byte data transfers. all data transfers are initiated by driving cs low. if cs is high, then dout is high impedance. serial clock (sclk) a clock cycle on sclk consists of a rising edge fol- lowed by a falling edge. for data input, data must be valid at din before the rising edge of the clock. for data outputs, bits are valid on dout after the falling edge of the clock. reading from the timekeeping registers the timekeeping registers (seconds, minutes, hours,date, month, day, and year) and the control register can be read either with a single read (figure 5) or a burst read (figure 6). since the rtc runs continuously and a read takes a finite amount of time, there is the possibility that the clock counters could change during a read operation, thereby reporting inaccurate time- keeping data. in the max6916, each clock counter s data is buffered by a latch. clock counter data islatched by the spi bus read command (on the falling edge of sclk after the address/command byte has been sent by the master to read a timekeeping regis- ter). collision-detection circuitry ensures that this does not happen coincident with a seconds counter update to ensure accurate time data is being read. this avoids time-data changes during a read operation. the clock counters continue to count and keep accurate time dur- ing the read operation. if single reads are used to read each of the timekeep-ing registers individually, then it is necessary to do some error checking on the receiving end. an error can occur when the seconds counter increments before all the other registers are read out. for example, suppose a carry of 13:59:59 to 14:00:00 occurs during single- read operations of the timekeeping registers. then the net data could become 14:59:59, which is erroneous real-time data. to prevent this with single-read opera- tions, read the seconds register first (initial seconds) and store this value for future comparison. when the remaining timekeeping registers have been read out, read the seconds register again (final seconds). if the initial seconds value is 59, check that the final-seconds value is still 59; if not, repeat the entire single-read process for the timekeeping registers. a comparison of the initial-seconds value with the final-seconds value can indicate if there was a bus-delay problem in read- ing the timekeeping data (difference should always be 1s or less). using a 2mhz bus speed, and sequential single reads, it would take under 75? to read all seven of the timekeeping registers plus a second read of the seconds register. the most accurate way to read the timekeeping regis- ters is to perform a burst read. with burst reads, the main timekeeping registers (seconds, minutes, hours, date, month, day, year) and the control register are read sequentially, in the order listed with the seconds register first. they must be all read out as a group of eight registers, with 8 bytes each, for proper execution of the burst-read function. all seven timekeeping regis- ters are latched upon the receipt of the burst-read com- mand. worst-case error that can occur between the actual time and the read time is 1s. cs sclk din dout a5 a4 a3 a2 a1 a0 1 address/command byte data byte 1 burst read a6 data byte n dout is high impedance d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 figure 6. spi interface multiple/burst read downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 15 writing to the timekeeping registers the time and date can be set by writing to the time- keeping registers (seconds, minutes, hours, date, month, day, year, and century). to avoid changing the current time by an incomplete write operation, the cur- rent time value is buffered from being written directly to the clock counters. the new data sent replaces the cur- rent contents of this input buffer. this time update data is loaded into the clock counters at the rising edge of cs , which indicates the end of the spi bus write opera- tion. collision-detection circuitry ensures that this doesnot happen coincident with a seconds-counter update to guarantee that accurate time data is being written. this avoids time data changes during a write operation. an incomplete write operation aborts the time-update procedures and the contents of the input buffer are dis- carded. the clock counter is reset immediately after a write to the seconds register or a burst write to the time- keeping registers. this process ensures that 1s clock tick is synchronous to timekeeping writes. if single-write operations (figure 3) are used to write to each of the timekeeping registers, then error checking is needed. if the seconds register is the one to be updat- ed, update it first and then read it back and store its value as the initial seconds. update the remaining time- keeping registers and then read the seconds register again (final seconds). if initial seconds was 59, ensure it is still 59. if initial seconds was not 59, ensure that final seconds is within 1s of initial seconds. if the seconds register is not to be written to, then read the seconds register first and save it as initial seconds. write to the required timekeeping registers and then read the sec- onds register again (final seconds). if initial seconds was 59, ensure it is still 59. if initial seconds was not 59, ensure that final seconds is within 1s of initial seconds. although both single writes and burst writes are possi- ble, the most accurate way to write to the timekeeping counters is to do a burst write (figure 4). in the burst write, the main timekeeping registers (seconds, min- utes, hours, date, month, day, year) and the control register are written sequentially. they must be all writ- ten to as a group of eight registers, with 8 bytes each, for proper execution of the burst-write function. all seven timekeeping registers and the control register are simultaneously loaded into the clock counters at the rising edge of cs , at the end of the spi bus write oper- ation. the worst-case error that can occur between theactual time and the write time update is 1s. to avoid rollover issues when writing time data to themax6916, the remaining time and date registers must be written within 1s of updating the seconds register when using single writes. for burst writes, all eight reg- isters must be written within this period (1s). the weekday data in the day register increments at midnight. values that correspond to the day of week are user defined, but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). if invalid values are written to the timekeeping registers, operation becomes undefined. registers tables 1 and 2 show the register map, as well as theregister descriptions for the max6916. control register the control register contains bits for configuring themax6916 for custom applications. bit d0 (batt on blink) and d1 (batt lo blink) are used to enable a 1hz blink rate on batt_on and batt_lo when they are active; see the battery test section for details. d2 (wd time) and d3 (wd en) are used to enable thewatchdog function and select its timeout. for details, see the watchdog input section. d5 (int/ext test) sets whether the internal resistor ratio or an externalresistor ratio is to be used to check for the low-battery condition; see the battery test section for details. d6 (xtal en) enables the crystal-fail-detect circuitry whenset. see the crystal-fail detect section for details. d7 (wp) is the write-protect bit. before any write operationto the registers (except the control register) or ram, bit 7 must be zero. when set to one, the write-protect bit prevents write operations to any register (except the control register) or ram locations. timekeeping and alarm thresholds registers time and date data is stored in the timekeeping andalarm threshold registers in bcd format as shown in table 1. the weekday data in the day register is user defined (a common format is 1 = sunday, 2 = monday, etc.). am-pm/12?4 mode for both timekeeping and alarm threshold registers(table 1), d7 of the hours register is defined as the 12hr or 24hr mode-select bit. when set to one, the 12hr mode is selected. in the 12hr mode, d5 is the am /pm bit with logic one being pm. in the 24hr mode, d5 is thesecond 10hr bit (20hr to 23hr). downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 16 ______________________________________________________________________________________ table 1. register map clock burst 0 000000 a0 a1 a2 a3 a4 a5 a6 a7 function d0 d1 d2 d3 d4 d5 d6 d7 0000000 value 000000 0 10 sec 1 sec 0?9 por state sec 0000000 000001 0 0 10 min 1 min 0?9 por state min 0 0 00 0 000001 0 12/24 10 hr 1 hr 00?3 por state hr am/pm 10 hr 000 01?2 0000000 000010 1 0 10 date 1 date 01?8/2901?0/31 por state date 0000000 000010 1 0 10 m 1 month 01?2 por state month 00 0000000 000011 1 0 weekday 01?7 por state day 0000 0111000 000011 0 1 year 00?9 por state year 10 year 0 01 0 000100 1 wp por state control int/ ext test 000 xtal en 0 wd en wd time batt lo blink batt on blink 0001100 000100 1 100 year 00?9 por state century 1000 year 0 00 0 000101 0 one sec por state alarm configuration day 000 year month date hr min sec 0 00 0 000110 0 xtal fail por state status batt lo 000 data valid alm out 0000 0 register address register function 0 por state defines the power-on reset state of the register r w 1 r w r w r w r w r w r w r w r w 01 0 1 0 1 0 r w r w r w 10 0 downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 17 table 1. register map (continued) batt test 0000110 a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 0111111 value 000111 1 10 sec 1 sec 059 por state sec 0111111 000111 1 0 10 min 1 min 059 por state min 0 1 10 1 001000 1 10 hr 1 hr 0023 por state hr 10 hr 111 0112 0011111 001000 1 0 10 date 1 date 01 28/29 01 30/31 por state date 0001111 001001 1 0 10 m 1 month 01 12 por state month 00 0000011 001001 1 0 weekday 01 07 por state day 0000 1111111 001010 1 1 year 00 99 por state year 10 year 001010 test configuration (factory reserved) xxxxxxx 001111 x ram data 0 00hffh ram data 95 00h ffh ram 0 111111 111111 0 register address register function 0 0000000 0 por state alarmthresholds: ram registers: xxxxxxx x ram 95 ram burst 1 por state defines the power-on reset state of the register w r w r w r w r w r w r w r w r w r w r w r 01 0 1 0 1 0 1 1 0 1 function 12/24 am/pm downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 18 ______________________________________________________________________________________ clock-burst mode addressing the clock-burst register specifies burst-mode operation. in this mode, the first eight clock/cal- endar registers (seven timekeeping and the control register) can be consecutively read or written to by using the address/command byte 00h for a write or 80h for a read (table 1). if the write-protect bit is set to one when a write-clock/calendar-burst mode is specified, no data transfer occurs to any of the seven timekeeping registers or the control register. when writing to the clock/calendar registers in the burst mode, the first eight registers must be written to for the data to be transferred; see table 2. ram the static ram consists of 96 x 8 bits addressed con-secutively in the ram address/command space. address/commands (1fh to 7eh) are used for ram writes and address/commands (9fh to feh) are used for ram reads (table 2). ram-burst mode sending the ram burst address/command (7fh forwrite, ffh for read) specifies burst-mode operation. in this mode, the 96 ram locations can be consecutively read or written to starting with bit 7 of address/com- mand 1fh for writes, and 9fh for reads. a burst read outputs all 96 bytes of ram. when writing to ram in burst mode, it is not necessary to write all 96 bytes for the data to transfer; each complete byte written is transferred to the ram. when reading from ram, data is output until all 96 bytes have been read, or until the cs is driven high. status register the status register contains individual bits for monitor-ing the status of several functions of the max6916. bits d0 d3 are unused and always read zero (table 1). d4 (alm out) reflects the state of the alarm function; seethe alarm function section for details. d5 (batt lo) indicates the state of the battery connected to v batt ; see the battery test section for more information. d6 (data valid) alerts the user if all power was lost. seethe data valid bit section for details. d7 (xtal fail) is the output of the crystal-fail detect circuit. see the crystal-fail detect section for details. power control v batt provides power as a battery backup. v cc pro- vides the primary power in dual-supply systems wherev batt is connected as a backup source to maintain timekeeping in the absence of primary power. whenv cc rises above the reset threshold, v rst , v cc powers the max6916. when v cc falls below the reset thresh- old, v rst , and is less than v trd , v batt powers the max6916. if v cc falls below the reset threshold, v rst , and is more than v tru , v cc still powers the max6916. the v cc slew rate in power-down is limited to 10v/ms (max) for proper data retention. v out function v out is an output supply voltage for battery-backed-up devices such as sram. when v cc rises above the reset threshold or is greater than v batt ,v out connects to v cc (figure 16). when v cc falls below v rst and v batt , v out connects to v batt . there is a typical ?00mv hysteresis associated with the switchingbetween v cc and v batt on the v out output. connect a 0.1? capacitor from v out to gnd. power-on reset (por) the max6916 contains an integral por circuit thatensures all registers are reset to a known state on power- up. once either v cc or v batt rises above 1.6v (typ), the por circuit releases the registers for normal operation.when v cc or v batt drops to less than 0.9v (typ), the max6916 resets all register contents to the por defaults. oscillator start time the max6916 oscillator typically takes 1s to 2s to beginoscillating. to ensure the oscillator is operating correct- ly, the system software should validate proper time- keeping. this validation is accomplished by reading the seconds register. any reading with more than 0s, from the por value of 0s, is a validation of proper startup. alarm-generation function the alarm function is configured using the alarm-con- figuration register and the alarm-threshold registers (tables 1 and 2). writing a one to d7 (one sec) in the alarm-configuration register sets the alarm function to occur once every second, regardless of any other set- ting in the alarm-configuration register or in any of the alarm-threshold registers. when the alarm is triggered, d4 (alm out) in the status register is set to one and the open-drain alarm output alm goes low. the alarm is cleared by reading or writing to the alarm-configura-tion register or by reading or writing to any of the alarm- threshold registers. this process resets the alm output to a high and the alm out bit to zero. when d7 (one sec) is set to zero in the alarm-configu- ration register, then the alarm function is set by the remaining bits in the alarm-configuration register and the contents of the respective alarm-threshold register. for example, writing 01h (0000 0001) to the alarm-con- figuration register causes the alarm to trigger every time the seconds-timekeeping register matches the seconds alarm-threshold register (i.e., once every minute on a specific second). writing 02h (0000 0010) to the alarm-configuration register causes the alarm to downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 19 trigger on a minutes match (i.e., once every hour).writing a 4fh (0100 1111) to the alarm configuration register causes the alarm to be triggered on a specific second, of a specific minute, of a specific hour, of aspecific date, of a specific year. when setting the alarm-threshold registers, ensure that table 2. hex register address and description write address/command (hex) read address/command (hex) description por setting (hex) 00 80 clock burst n/a 01 81 seconds 00 02 82 minutes 00 03 83 hour 00 04 84 date 01 05 85 month 01 06 86 day 01 07 87 year 70 08 88 control 48 09 89 century 19 0a 8a alarm configuration 00 0c 8c status 00 0d n/a battery test n/a 0e 8e seconds alarm threshold 7f 0f 8f minutes alarm threshold 7f 10 90 hours alarm threshold bf 11 91 date alarm threshold 3f 12 92 month alarm threshold 1f 13 93 day alarm threshold 07 14 94 year alarm threshold ff 15 95 test configuration 00 1f 9f ram 0 indeterminate 20 a0 ram 1 indeterminate 21 a1 ram 2 indeterminate 22 a2 ram 3 indeterminate 23 a3 ram 4 indeterminate ???? ???? ???? 7a fa ram 91 indeterminate 7b fb ram 92 indeterminate 7c fc ram 93 indeterminate 7d fd ram 94 indeterminate 7e fe ram 95 indeterminate 7f ff ram burst n/a downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 20 ______________________________________________________________________________________ both the hour-timekeeping register and the hour-alarm-threshold register are using the same hour format (either 12hr or 24hr format). the alarm function as well as the alm output are oper- ational in both v cc and battery-backup mode. crystal-fail detect the crystal-fail detect circuit looks for a loss of oscillationfrom the 32.768khz oscillator for 30 cycles (typ) or more. both the control register and the status register are used in the crystal-failure detection scheme (table 1). the crystal-fail detect circuit sets the xtal fail bit in the status register to one for a crystal failure and to zero for normal operation. once the status register is read, the xtal fail bit is reset to zero, if it was previously one. if the crystal-fail-detect circuit continues to sense a failed crystal, then the xtal fail bit is set again. on initial power-up, the crystal-fail detect circuit is enabled. since it takes a while for the low-power, 32.768khz oscillator to start, the xtal fail bit in the status register can be set to one, indicating a crystal failure. the xtal fail bit should be polled a number of times to see if it is set to zero for successive polls. if the polling is far enough apart, a few polled results could guarantee that a maximum of 10s had elapsed since power-on, at which time the oscillator would be consid- ered truly failed if the xtal fail bit remains one. on subsequent power-ups, when xtal en is set to one, if xtal fail is set to one, time data should be considered suspect. the crystal-fail-detection circuit functions in both v cc and v batt modes when the xtal en bit is set in the control register. manual reset input a logic-low on mr asserts reset . reset remains asserted while mr is low, and for t rp after it returns high (figure 7). mr has an internal pullup resistor, so it can be left open if it is not used. internal debounce cir- cuitry requires a minimum low time on the mr input of 1? with 35ns maximum glitch immunity. reset output a microprocessor s (? s) reset input starts the ? in a known state. the max6916 s ? supervisory circuit asserts a reset to prevent code-execution errors duringpower-up, power-down, and brownout conditions. the reset output is guaranteed to be active for 0v < v cc < v rst , provided v batt is greater than v batt (min). if v cc drops below and then exceeds the reset threshold, an internal timer keeps reset active for the reset timeout period t rp ; after this interval, reset becomes inactive high. this condition occurs at either power-upor after a v cc brownout. the reset output is also activated when the watchdog interrupt function is enabled but no transition is detect-ed on the wdi input. in this case, reset is active for the period t rp before becoming inactive again. when reset is active, all inputs wdi, mr , ce_in , din, cs , and sclk are disabled. dout is also disabled. the max6916eo30 is optimized to monitor 3.0v ?0%power supplies. except when mr is asserted, reset is not active until v cc falls below 2.7v (3.0v - 10%), but is guaranteed to occur before the power supply fallsbelow 2.5v (3.0v - 15%). the max6916eo33 is optimized to monitor 3.3v ?0% power supplies. except when mr is asserted, reset is not active until v cc falls below 3.0v (3.0v is just above 3.3v - 10%), but is guaranteed to occur before thepower supply falls below 2.8v (3.3v - 15%). the MAX6916EO50 is optimized to monitor 5.0v ?0% power supplies. except when mr is asserted, reset is not active until v cc falls below 4.5v (5.0v - 10%), but is guaranteed to occur before the power supply fallsbelow 4.2v (4.2v is just below 5.0v - 15%). negative-going v cc transients the max6916 is relatively immune to short-durationnegative transients (glitches) while issuing resets to the ? during power-up, power-down, and brownout condi- tions. therefore, resetting the ? when v cc experi- ences only small glitches is usually not recommended.typically, a v cc transient that goes 150mv below the reset threshold and lasts for 50? or less does not cause a reset pulse to be issued. a 0.1? capacitor mounted close to the v cc pin provides additional tran- sient immunity. mr ce out ce in reset t rce t rp t rp figure 7. manual reset timing diagram downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 21 interfacing to microprocessors with bidirectional reset pins microprocessors with bidirectional reset pins, such asthe motorola 68hc11 series, can contend with the max6916 reset output. if, for example, the reset output is driven high and the ? wants to pull it low,indeterminate logic levels can result. to correct this, connect a 4.7k resistor between the reset output and the ? reset i/o as shown in figure 8. buffer thereset output to other system components. battery-on output the battery-on output, batt_on , is an open-drain out- put that indicates when the max6916 is powered fromthe backup-battery input, v batt . when v cc falls below the reset threshold, v rst , and below v batt , v out switches from v cc to v batt and batt_on becomes low. when v cc rises above the reset threshold, v rst , v out reconnects to v cc and batt_on becomes high (open-drain output with pullup resistor). if desired, thebatt_on output can be register selected, through the batt on blink bit in the control register, to toggle onand off (0.5s on, 0.5s off) when active. the por default is logic zero for no blink. watchdog input the watchdog circuit monitors the ? s activity. if the ? does not toggle the watchdog input (wdi) within theregister-selectable watchdog-timeout period, reset is asserted for t rp . at the same time, the wd en and wd time bits in the control register (table 1) are reset to zero and can only be set again by writing the appropri- ate command to the control register. thus, once a reset is asserted due to a watchdog timeout, the watchdog function is disabled (figure 9). wdi can detect pulses as short as t wdi . data bit d2 in the control register controls the selection of the watch- dog-timeout period. the power-up default is 1.6s (d2 = 0). a reset condition returns the timeout to 1.6s (d2 = 0). if d2 is set to one, then the watchdog-timeout period is changed to 200ms. data bit d3 in the control register is the watchdog-enable function. a logic zero dis- ables the watchdog function, while a logic one enables it. the por state of wd en is logic one, or the watchdog function is enabled. disable the watchdog function by writing a zero to the wd en bit in the control register, within the 1.6s por default timeout after power-up. wdi does not include a pulldown or pullup feature. for this reason, wdi should not be left floating. when the wd en bit in the control register is set to zero, wdi should be connected to v cc or gnd. wdi is disabled and does not draw cross-conduction current when v cc falls below v rst . watchdog software considerations there is a way to help the watchdog-timer monitor soft- ware execution more closely, which involves setting and resetting the watchdog input at different points in the program rather than pulsing the watchdog input. this technique avoids a stuck loop, in which the watchdog timer would continue to be reset within the loop, keepingthe watchdog from timing out. figure 10 shows an example of a flow diagram where the i/o driving the watchdog input is set high at the beginning of the pro- gram, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. if the program should hang in any sub- routine, the problem would quickly be corrected sincethe i/o is continually set low and the watchdog timer is allowed to time out, causing a reset to be issued. max6916 v cc gnd v cc gnd reset reset buffer 4.7k p v cc figure 8. interfacing to ? with bidirectional reset i/o v rst v cc reset wdi t rp t rp t wd t wd wd en and wd time are setto zero and the watchdog function is disabled. figure 9. watchdog timing diagram downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 22 ______________________________________________________________________________________ chip-enable gating internal gating of chip-enable (ce) signals preventserroneous data from corrupting external sram in the event of an undervoltage condition. the max6916 uses a transmission gate from ce_in to ce_out (figure 11). during normal operation ( reset inactive), the transmis- sion gate is enabled and passes all ce transitions.when reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the external sram. the short ce propagation delay from ce_in to ce_out enables the max6916 to be used with most microprocessors. if ce_in is low when reset asserts, ce_out remains low for t rce to permit completion of the current write cycle. chip-enable input the ce transmission gate is disabled and ce_in is high impedance (disabled mode) while reset is active. during a power-down sequence when v cc passes the reset threshold, the ce transmission gatedisables and ce_in immediately becomes high imped- ance if the voltage at ce_in is high. if ce_in is low when reset becomes active, the ce transmission gate disables at the moment ce_in goes high or t rce after reset is active, whichever occurs first (see the chip- enable timing section). this condition permits the cur- rent write cycle to complete during power-down. thece transmission gate remains disabled and ce_in remains high impedance (regardless of ce_in activity) for most of the reset-timeout period (t rst ) any time a reset is generated. when the ce transmission gate is enabled, the impedance of ce_in appears as a 46 (typ) load in series with the load at ce_out . the propagation delay through the ce transmissiongate depends on v cc , the source impedance of the driver connected to ce_in , and the loading on ce_out (see the chip-enable propagation delay vs. ce_out load capacitance graph in the typical operating characteristics ). for minimum propagation delay, the capacitive load at ce_out should be mini- mized, and a low-output-impedance driver should beused on ce_in (figure 12). start set wdi high program code subroutine of program loop set wdi low return figure 10. watchdog flow diagram max6916 chip-enable output control reset generator v out ce_out ce_in figure 11. chip-enable gating max6916 25 equivalent source impedance 50 cable 50 3.6v v cc c l 10pf gnd v cc 50 ce_in ce_out batt c l includes load capacitance and scope probe capacitance figure 12. propagation delay test circuit downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 23 chip-enable output when the ce transmission gate is enabled, the imped-ance seen at ce_out is equivalent to a 46 (typ) resistor in series with the source driving ce_in . in the disabled mode, the transmission gate is off and anactive pullup connects ce_out to v out (see figures 11 and 13). this pullup turns off when the transmissiongate is enabled. test configuration register this is a read-only register. data valid bit data valid has a por setting of zero, indicating thatthe data in the max6916 rtc is not guaranteed to be valid (table 1). a read of the status register sets the data valid bit to one, indicating valid data in the max6916 rtc. in a system that uses a backup power supply, the data valid bit should be set to one by the system software on first system power-up by reading the status register. after that, any time the system recovers from a reset condition caused by v cc < v rst , the data valid bit can be read to see if the data stored during operation from the backup power supply is still valid (i.e.,the backup power supply did not drop out). a one indi- cates valid data, and a zero indicates corrupted data. any time the internal supply to the max6916 (either v batt or v cc depending upon the operating conditions) drops below 1.5v to 1.6v (typ), the data valid bit is setto zero even if it has recently been set by a read of the status register. battery test battery-test normal operation in normal operation, the battery-test circuitry uses thecontrol register por settings of int/ext test, which is set to logic-low as default (table 1). in this mode, all bat- tery-test load resistors and threshold settings are internal. when v cc rises above v rst , the max6916 automatically performs one power-on battery monitor test. additionally,a battery check is performed every time that a reset is issued, either from a manual reset or from a watchdog timeout. after that, periodic battery voltage monitoring at the factory-programmed time interval of 24hr begins while v cc is applied. v cc reset ce_out ce_in 2.0v v rst t rp t rp v batt v cc t ced t rce t rpd v rst figure 13. chip-enable timing diagram downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 24 ______________________________________________________________________________________ after each 24hr period (t btcn ) has elapsed, the max6916 connects v batt to an internal 0.91m (typ) test resistor (r set+_int + r set-_int ) for 1s (t btpw ) (figure 14). during this 1s, if v batt falls below the fac- tory-programmed battery trip point v btp , the open- drain, battery-low output, batt_lo , is asserted active low and the batt lo bit in the status register is set toone. the batt lo output can be register selected to toggle at a 1hz rate (0.5s on, 0.5s off) when active.once batt lo is active, the 24hr tests stop until a fresh battery is inserted and batt lo is cleared by writing any data to the battery test register at address0x0d (figure 15). writing to this register performs a battery test and provided that the fresh battery is not low, deactivates the batt lo output and resets batt lo in the status register. normal 24hr testing resumes.if a different load or batt lo thresholds are desired for testing the backup battery, then external program resis-tors can be used in conjunction with the trip and test inputs (see the battery-test control register and other test options section). battery replacement following batt_lo activation should be done with v cc nominal and not in battery- backup mode so that sram data is not lost.alternatively, if sram data need not be saved, the bat- tery can be replaced with the v cc supply removed. if a battery is replaced in battery-backup mode, sufficienttime must be allowed for the voltage on the v out out- put to decay to zero. this timing ensures that the fresh-ness-seal mode of operation has been reset and is active when v cc is powered up again. if insufficient time is allowed, then v cc must exceed v batt during the subsequent power-up to ensure that the max6916has left battery-backup mode (figure 16). the max6916 does not constantly monitor an attached battery because such monitoring would drastically reduce the life of the battery. as a result, the max6916 only tests the battery for 1s every 24hr. if a good bat- tery (one that has not been previously flagged with batt_lo ) is removed between battery tests, the max6916 does not immediately sense the removal anddoes not activate batt_lo until the next-scheduled battery test. for this reason, a software-commandedbattery test should be performed after a battery replacement by writing any data to the battery-test reg- ister at address 0dh. max6916 1.24v v cc batt_lo control logic r set+_int 480k r set-_int 430k v out int/ext test = 0 ( 5ma) batt test test trip v batt batt_lo r set+_ext r load_ext (optional) r set-_ext q ext int/exttest figure 14. max6916 battery load and test circuit downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 25 battery monitoring is only a useful technique when test-ing can be done regularly over the entire life of a lithium battery. because the max6916 only performs battery monitoring when v cc is nominal, systems that are pow- ered down for excessively long periods can completelydrain their lithium cells without receiving any advanced warning. to prevent such an occurrence, systems using the max6916 battery-monitoring feature should be powered up periodically (at least every few months) in order to perform battery testing. furthermore, any- time batt_lo is activated on the first battery test after a power-up, data integrity should be checked througha checksum or other technique. timekeeping data would also be suspect and should be checked for accuracy against an accurate known reference. freshness-seal mode when the battery is first attached to the max6916 with-out v cc power applied, the device does not immediate- ly provide battery-backup power to v out (figure 16). only after v cc exceeds v rst and later falls below both v rst and v batt does the max6916 leave freshness- seal mode and provide battery-backup power. thismode allows a battery to be attached during manufac- turing but not used until after the system has been acti- vated for the first time. as a result, no battery energy is drained during storage and shipping. t btcn t btpw t bl once the battery is detected as low, the periodic battery testing ceases. a battery check can be initiated by writing to the register 0x0d. v rst v cc v batt battery- test active batt_lo v btp (battery test point) figure 15. battery test timing diagram v cc v batt 0v v out 0v v rst v batt v rst v rst v rst exit freshnessseal mode freshnessseal reset v batt connected to v out v cc connected to v out v batt connected to v out v cc connected to v out v batt connected to v out v batt floating v batt floating battery attach battery detach battery attach battery detach figure 16. battery switchover diagram downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller 26 ______________________________________________________________________________________ battery-test control register and other test options there are two warning formats for the batt_lo and batt_on outputs. by setting d0 (batt on blink) and/or d1 (batt lo blink) in the control register toone, the respective warning output toggles on every 0.5s and off every 0.5s when set to active low by the internal max6916 logic. this setting allows a more noticeable warning indicator in systems where an led is connected as a status or warning light for the end user. the por default settings of zero leave these out- puts set to logic-low when they are active. d5 (int/ext test) selects whether the battery test cir- cuit is configured as internal or external (table 1). if d5 is set to zero (default value), then the internal resistor- divider is used between v batt and gnd to select the battery-low trip point (figure 14). the internal resistors,r set+_int and r set-_int , are used to divide v batt in half, as well as to provide the battery-test-load resis- tance of 0.91m (typ). if d5 (int/ext test) is set to one, then the two externalresistors, r set+_ext and r set-_ext , are used to divide v batt down to the ratio for a trip point set at trip of 1.24v (v trip ) (typ). r set+_ext plus r set-_ext in series provide the load resistance used during the 1s every-24hr-battery test. if additional load resistance is desired, then an external load resistor, r load_ext , can be placed between v batt and the collector or drain of the transistor driven by test. the equivalent load resis-tance used to test the battery is then r load_ext in par- allel with the series combination of r set+_ext plus r set-_ext . in this mode, the internal resistors are removed from trip and are not used as a load duringthe battery-test pulse. test pulses high to perform the battery test and remains low between tests. one final battery-test feature of the max6916 is thesoftware write address/command of 0dh that forces a 1s battery test to be performed every time it is sent. applications information crystal selection connect a 32.768khz watch crystal directly to themax6916 through pins 9 and 10 (x1, x2) (figure 17). use a crystal with a specified load capacitance (c l ) of 6pf. refer to applications note 616: considerations for maxim real-time clock crystal selection from the maxim website (www.maxim-ic.com) for more informa-tion regarding crystal parameters and crystal selection, as well as a list of crystal manufacturers. when designing the pc board, keep the crystal as close to the x1 and x2 pins of the max6916 as possible. keep the trace lengths short and small to reduce capacitive loading and prevent unwanted noise pickup. place a guard ring around the crystal and connect the ring to ground to help isolate the crystal from unwanted noise pickup. keep all signals out from beneath the crystal and the x1 and x2 pins to prevent noise coupling. finally, an additional local ground plane on an adjacent pc board layer can be added under the crystal to shield it from unwanted pickup from traces on other layers of the board. this plane should be isolated from the regular pc board ground, connected to the gnd pin of the max6916, and needs to be no larger than the perimeter of the guard ring. ensure that this ground plane does not contribute to sig- nificant capacitance between the signal line and ground on the connections that run from x1 and x2 to the crystal. see figure 18. r d c d 12pf c g 12pf external crystal x1 x2 max6916 r f figure 17. oscillator functional schematic * * * * * * * * * **** ** x2 * guard ring ground plane via connection ground plane via connection sm watch crystal *layer 1 trace * **layer 2 local ground plane connect only to pin 8 ground plane via connection max6916 x1 groundplane via connection figure 18. crystal layout downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller ______________________________________________________________________________________ 27 for frequency stability over temperature, refer to theapplications note 617: real-time-clock selection and optimization from the maxim website (www.maxim-ic.com.) chip information process: cmos 2019 18 17 16 15 14 13 12 3 4 5 6 7 8 v batt v cc resetbatt_lo batt_on trip test v out top view ce_outalm sclk dout gnd wdi mr ce_in 1211 9 10 csdin x2 x1 max6916 qsop + pin configuration user reset n 3.3v 3.3v 3.3v 3.3v led n.c. crystal 3.3v 0.1 f 0.1 f 3.0v 0.1 f n.c. n.c. batt_lo batt_on x1 x2 v cc v batt mr alm cs dout din sclk reset ce_in wdi trip test v out ce_out max6916 gnd gnd ce i/o p1.0 rst sck mosi miso ss into c gnd cmos sram typical application circuit part supply voltage (v) max6916eo30 3.0 max6916eo33 3.3 MAX6916EO50 5.0 selector guide downloaded from: http:///
max6916 spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qsop.eps e 1 1 21-0055 package outline, qsop .150", .025" lead pitch downloaded from: http:///

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